IEC 62530-2:2021
SystemVerilog - Part 2: Universal Verification Methodology Language Reference Manual
IEC 62530-2:2021(E) establishes the Universal Verification Methodology (UVM), a set of application programming
interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™. This publication has the status of a double logo IEC/IEEE standard.
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